#include <PR/R4300.h>
#include <PR/ultratypes.h>

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Macros
#define	RDRAM_0_START 0x00000000

#define	RDRAM_0_END 0x001FFFFF

#define	RDRAM_1_START 0x00200000

#define	RDRAM_1_END 0x003FFFFF

#define	RDRAM_START RDRAM_0_START

#define	RDRAM_END RDRAM_1_END

#define	RDRAM_BASE_REG 0x03F00000

#define	RDRAM_CONFIG_REG (RDRAM_BASE_REG+0x00)

#define	RDRAM_DEVICE_TYPE_REG (RDRAM_BASE_REG+0x00)

#define	RDRAM_DEVICE_ID_REG (RDRAM_BASE_REG+0x04)

#define	RDRAM_DELAY_REG (RDRAM_BASE_REG+0x08)

#define	RDRAM_MODE_REG (RDRAM_BASE_REG+0x0c)

#define	RDRAM_REF_INTERVAL_REG (RDRAM_BASE_REG+0x10)

#define	RDRAM_REF_ROW_REG (RDRAM_BASE_REG+0x14)

#define	RDRAM_RAS_INTERVAL_REG (RDRAM_BASE_REG+0x18)

#define	RDRAM_MIN_INTERVAL_REG (RDRAM_BASE_REG+0x1c)

#define	RDRAM_ADDR_SELECT_REG (RDRAM_BASE_REG+0x20)

#define	RDRAM_DEVICE_MANUF_REG (RDRAM_BASE_REG+0x24)

#define	RDRAM_0_DEVICE_ID 0

#define	RDRAM_1_DEVICE_ID 1

#define	RDRAM_RESET_MODE 0

#define	RDRAM_ACTIVE_MODE 1

#define	RDRAM_STANDBY_MODE 2

#define	RDRAM_LENGTH (25122048)

#define	RDRAM_0_BASE_ADDRESS (RDRAM_0_DEVICE_ID*RDRAM_LENGTH)

#define	RDRAM_1_BASE_ADDRESS (RDRAM_1_DEVICE_ID*RDRAM_LENGTH)

#define	RDRAM_0_CONFIG 0x00000

#define	RDRAM_1_CONFIG 0x00400

#define	RDRAM_GLOBAL_CONFIG 0x80000

#define	PIF_ROM_START 0x1FC00000

#define	PIF_ROM_END 0x1FC007BF

#define	PIF_RAM_START 0x1FC007C0

#define	PIF_RAM_END 0x1FC007FF

#define	CHNL_ERR_NORESP 0x80 /* Bit 7 (Rx): No response error */

#define	CHNL_ERR_OVERRUN 0x40 /* Bit 6 (Rx): Overrun error */

#define	CHNL_ERR_FRAME 0x80 /* Bit 7 (Tx): Frame error */

#define	CHNL_ERR_COLLISION 0x40 /* Bit 6 (Tx): Collision error */

#define	CHNL_ERR_MASK 0xC0 /* Bit 6-7: channel errors */

#define	DEVICE_TYPE_CART 0 /* ROM cartridge */

#define	DEVICE_TYPE_BULK 1 /* ROM bulk */

#define	DEVICE_TYPE_64DD 2 /* 64 Disk Drive */

#define	DEVICE_TYPE_SRAM 3 /* SRAM */

#define	SP_DMEM_START 0x04000000 /* read/write */

#define	SP_DMEM_END 0x04000FFF

#define	SP_IMEM_START 0x04001000 /* read/write */

#define	SP_IMEM_END 0x04001FFF

#define	SP_BASE_REG 0x04040000

#define	SP_MEM_ADDR_REG (SP_BASE_REG+0x00) /* Master */

#define	SP_DRAM_ADDR_REG (SP_BASE_REG+0x04) /* Slave */

#define	SP_RD_LEN_REG (SP_BASE_REG+0x08) /* R/W: read len */

#define	SP_WR_LEN_REG (SP_BASE_REG+0x0C) /* R/W: write len */

#define	SP_STATUS_REG (SP_BASE_REG+0x10)

#define	SP_DMA_FULL_REG (SP_BASE_REG+0x14)

#define	SP_DMA_BUSY_REG (SP_BASE_REG+0x18)

#define	SP_SEMAPHORE_REG (SP_BASE_REG+0x1C)

#define	SP_PC_REG 0x04080000

#define	SP_DMA_DMEM 0x0000 /* Bit 12: 0=DMEM, 1=IMEM */

#define	SP_DMA_IMEM 0x1000 /* Bit 12: 0=DMEM, 1=IMEM */

#define	SP_CLR_HALT 0x00001 /* Bit 0: clear halt */

#define	SP_SET_HALT 0x00002 /* Bit 1: set halt */

#define	SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */

#define	SP_CLR_INTR 0x00008 /* Bit 3: clear intr */

#define	SP_SET_INTR 0x00010 /* Bit 4: set intr */

#define	SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */

#define	SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */

#define	SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */

#define	SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */

#define	SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */

#define	SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */

#define	SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */

#define	SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */

#define	SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */

#define	SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */

#define	SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */

#define	SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */

#define	SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */

#define	SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */

#define	SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */

#define	SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */

#define	SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */

#define	SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */

#define	SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */

#define	SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */

#define	SP_STATUS_HALT 0x001 /* Bit 0: halt */

#define	SP_STATUS_BROKE 0x002 /* Bit 1: broke */

#define	SP_STATUS_DMA_BUSY 0x004 /* Bit 2: dma busy */

#define	SP_STATUS_DMA_FULL 0x008 /* Bit 3: dma full */

#define	SP_STATUS_IO_FULL 0x010 /* Bit 4: io full */

#define	SP_STATUS_SSTEP 0x020 /* Bit 5: single step */

#define	SP_STATUS_INTR_BREAK 0x040 /* Bit 6: interrupt on break */

#define	SP_STATUS_SIG0 0x080 /* Bit 7: signal 0 set */

#define	SP_STATUS_SIG1 0x100 /* Bit 8: signal 1 set */

#define	SP_STATUS_SIG2 0x200 /* Bit 9: signal 2 set */

#define	SP_STATUS_SIG3 0x400 /* Bit 10: signal 3 set */

#define	SP_STATUS_SIG4 0x800 /* Bit 11: signal 4 set */

#define	SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */

#define	SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */

#define	SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */

#define	SP_CLR_YIELD SP_CLR_SIG0

#define	SP_SET_YIELD SP_SET_SIG0

#define	SP_STATUS_YIELD SP_STATUS_SIG0

#define	SP_CLR_YIELDED SP_CLR_SIG1

#define	SP_SET_YIELDED SP_SET_SIG1

#define	SP_STATUS_YIELDED SP_STATUS_SIG1

#define	SP_CLR_TASKDONE SP_CLR_SIG2

#define	SP_SET_TASKDONE SP_SET_SIG2

#define	SP_STATUS_TASKDONE SP_STATUS_SIG2

#define	SP_CLR_RSPSIGNAL SP_CLR_SIG3

#define	SP_SET_RSPSIGNAL SP_SET_SIG3

#define	SP_STATUS_RSPSIGNAL SP_STATUS_SIG3

#define	SP_CLR_CPUSIGNAL SP_CLR_SIG4

#define	SP_SET_CPUSIGNAL SP_SET_SIG4

#define	SP_STATUS_CPUSIGNAL SP_STATUS_SIG4

#define	SP_IBIST_REG 0x04080004

#define	SP_IBIST_CHECK 0x01 /* Bit 0: BIST check */

#define	SP_IBIST_GO 0x02 /* Bit 1: BIST go */

#define	SP_IBIST_CLEAR 0x04 /* Bit 2: BIST clear */

#define	SP_IBIST_DONE 0x04 /* Bit 2: BIST done */

#define	SP_IBIST_FAILED 0x78 /* Bit [6:3]: BIST fail */

#define	DPC_BASE_REG 0x04100000

#define	DPC_START_REG (DPC_BASE_REG+0x00)

#define	DPC_END_REG (DPC_BASE_REG+0x04)

#define	DPC_CURRENT_REG (DPC_BASE_REG+0x08)

#define	DPC_STATUS_REG (DPC_BASE_REG+0x0C)

#define	DPC_CLOCK_REG (DPC_BASE_REG+0x10)

#define	DPC_BUFBUSY_REG (DPC_BASE_REG+0x14)

#define	DPC_PIPEBUSY_REG (DPC_BASE_REG+0x18)

#define	DPC_TMEM_REG (DPC_BASE_REG+0x1C)

#define	DPC_CLR_XBUS_DMEM_DMA 0x0001 /* Bit 0: clear xbus_dmem_dma */

#define	DPC_SET_XBUS_DMEM_DMA 0x0002 /* Bit 1: set xbus_dmem_dma */

#define	DPC_CLR_FREEZE 0x0004 /* Bit 2: clear freeze */

#define	DPC_SET_FREEZE 0x0008 /* Bit 3: set freeze */

#define	DPC_CLR_FLUSH 0x0010 /* Bit 4: clear flush */

#define	DPC_SET_FLUSH 0x0020 /* Bit 5: set flush */

#define	DPC_CLR_TMEM_CTR 0x0040 /* Bit 6: clear tmem ctr */

#define	DPC_CLR_PIPE_CTR 0x0080 /* Bit 7: clear pipe ctr */

#define	DPC_CLR_CMD_CTR 0x0100 /* Bit 8: clear cmd ctr */

#define	DPC_CLR_CLOCK_CTR 0x0200 /* Bit 9: clear clock ctr */

#define	DPC_STATUS_XBUS_DMEM_DMA 0x001 /* Bit 0: xbus_dmem_dma */

#define	DPC_STATUS_FREEZE 0x002 /* Bit 1: freeze */

#define	DPC_STATUS_FLUSH 0x004 /* Bit 2: flush */

#define	DPC_STATUS_START_GCLK 0x008 /* Bit 3: start gclk */

#define	DPC_STATUS_TMEM_BUSY 0x010 /* Bit 4: tmem busy */

#define	DPC_STATUS_PIPE_BUSY 0x020 /* Bit 5: pipe busy */

#define	DPC_STATUS_CMD_BUSY 0x040 /* Bit 6: cmd busy */

#define	DPC_STATUS_CBUF_READY 0x080 /* Bit 7: cbuf ready */

#define	DPC_STATUS_DMA_BUSY 0x100 /* Bit 8: dma busy */

#define	DPC_STATUS_END_VALID 0x200 /* Bit 9: end valid */

#define	DPC_STATUS_START_VALID 0x400 /* Bit 10: start valid */

#define	DPS_BASE_REG 0x04200000

#define	DPS_TBIST_REG (DPS_BASE_REG+0x00)

#define	DPS_TEST_MODE_REG (DPS_BASE_REG+0x04)

#define	DPS_BUFTEST_ADDR_REG (DPS_BASE_REG+0x08)

#define	DPS_BUFTEST_DATA_REG (DPS_BASE_REG+0x0C)

#define	DPS_TBIST_CHECK 0x01 /* Bit 0: BIST check */

#define	DPS_TBIST_GO 0x02 /* Bit 1: BIST go */

#define	DPS_TBIST_CLEAR 0x04 /* Bit 2: BIST clear */

#define	DPS_TBIST_DONE 0x004 /* Bit 2: BIST done */

#define	DPS_TBIST_FAILED 0x7F8 /* Bit [10:3]: BIST fail */

#define	MI_BASE_REG 0x04300000

#define	MI_INIT_MODE_REG (MI_BASE_REG+0x00)

#define	MI_MODE_REG MI_INIT_MODE_REG

#define	MI_CLR_INIT 0x0080 /* Bit 7: clear init mode */

#define	MI_SET_INIT 0x0100 /* Bit 8: set init mode */

#define	MI_CLR_EBUS 0x0200 /* Bit 9: clear ebus test */

#define	MI_SET_EBUS 0x0400 /* Bit 10: set ebus test mode */

#define	MI_CLR_DP_INTR 0x0800 /* Bit 11: clear dp interrupt */

#define	MI_CLR_RDRAM 0x1000 /* Bit 12: clear RDRAM reg */

#define	MI_SET_RDRAM 0x2000 /* Bit 13: set RDRAM reg mode */

#define	MI_MODE_INIT 0x0080 /* Bit 7: init mode */

#define	MI_MODE_EBUS 0x0100 /* Bit 8: ebus test mode */

#define	MI_MODE_RDRAM 0x0200 /* Bit 9: RDRAM reg mode */

#define	MI_VERSION_REG (MI_BASE_REG+0x04)

#define	MI_NOOP_REG MI_VERSION_REG

#define	MI_INTR_REG (MI_BASE_REG+0x08)

#define	MI_INTR_MASK_REG (MI_BASE_REG+0x0C)

#define	MI_INTR_SP 0x01 /* Bit 0: SP intr */

#define	MI_INTR_SI 0x02 /* Bit 1: SI intr */

#define	MI_INTR_AI 0x04 /* Bit 2: AI intr */

#define	MI_INTR_VI 0x08 /* Bit 3: VI intr */

#define	MI_INTR_PI 0x10 /* Bit 4: PI intr */

#define	MI_INTR_DP 0x20 /* Bit 5: DP intr */

#define	MI_INTR_MASK_CLR_SP 0x0001 /* Bit 0: clear SP mask */

#define	MI_INTR_MASK_SET_SP 0x0002 /* Bit 1: set SP mask */

#define	MI_INTR_MASK_CLR_SI 0x0004 /* Bit 2: clear SI mask */

#define	MI_INTR_MASK_SET_SI 0x0008 /* Bit 3: set SI mask */

#define	MI_INTR_MASK_CLR_AI 0x0010 /* Bit 4: clear AI mask */

#define	MI_INTR_MASK_SET_AI 0x0020 /* Bit 5: set AI mask */

#define	MI_INTR_MASK_CLR_VI 0x0040 /* Bit 6: clear VI mask */

#define	MI_INTR_MASK_SET_VI 0x0080 /* Bit 7: set VI mask */

#define	MI_INTR_MASK_CLR_PI 0x0100 /* Bit 8: clear PI mask */

#define	MI_INTR_MASK_SET_PI 0x0200 /* Bit 9: set PI mask */

#define	MI_INTR_MASK_CLR_DP 0x0400 /* Bit 10: clear DP mask */

#define	MI_INTR_MASK_SET_DP 0x0800 /* Bit 11: set DP mask */

#define	MI_INTR_MASK_SP 0x01 /* Bit 0: SP intr mask */

#define	MI_INTR_MASK_SI 0x02 /* Bit 1: SI intr mask */

#define	MI_INTR_MASK_AI 0x04 /* Bit 2: AI intr mask */

#define	MI_INTR_MASK_VI 0x08 /* Bit 3: VI intr mask */

#define	MI_INTR_MASK_PI 0x10 /* Bit 4: PI intr mask */

#define	MI_INTR_MASK_DP 0x20 /* Bit 5: DP intr mask */

#define	VI_BASE_REG 0x04400000

#define	VI_STATUS_REG (VI_BASE_REG+0x00)

#define	VI_CONTROL_REG VI_STATUS_REG

#define	VI_ORIGIN_REG (VI_BASE_REG+0x04)

#define	VI_DRAM_ADDR_REG VI_ORIGIN_REG

#define	VI_WIDTH_REG (VI_BASE_REG+0x08)

#define	VI_H_WIDTH_REG VI_WIDTH_REG

#define	VI_INTR_REG (VI_BASE_REG+0x0C)

#define	VI_V_INTR_REG VI_INTR_REG

#define	VI_CURRENT_REG (VI_BASE_REG+0x10)

#define	VI_V_CURRENT_LINE_REG VI_CURRENT_REG

#define	VI_BURST_REG (VI_BASE_REG+0x14)

#define	VI_TIMING_REG VI_BURST_REG

#define	VI_V_SYNC_REG (VI_BASE_REG+0x18)

#define	VI_H_SYNC_REG (VI_BASE_REG+0x1C)

#define	VI_LEAP_REG (VI_BASE_REG+0x20)

#define	VI_H_SYNC_LEAP_REG VI_LEAP_REG

#define	VI_H_START_REG (VI_BASE_REG+0x24)

#define	VI_H_VIDEO_REG VI_H_START_REG

#define	VI_V_START_REG (VI_BASE_REG+0x28)

#define	VI_V_VIDEO_REG VI_V_START_REG

#define	VI_V_BURST_REG (VI_BASE_REG+0x2C)

#define	VI_X_SCALE_REG (VI_BASE_REG+0x30)

#define	VI_Y_SCALE_REG (VI_BASE_REG+0x34)

#define	VI_CTRL_TYPE_16 0x00002 /* Bit [1:0] pixel size: 16 bit */

#define	VI_CTRL_TYPE_32 0x00003 /* Bit [1:0] pixel size: 32 bit */

#define	VI_CTRL_GAMMA_DITHER_ON 0x00004 /* Bit 2: default = on */

#define	VI_CTRL_GAMMA_ON 0x00008 /* Bit 3: default = on */

#define	VI_CTRL_DIVOT_ON 0x00010 /* Bit 4: default = on */

#define	VI_CTRL_SERRATE_ON 0x00040 /* Bit 6: on if interlaced */

#define	VI_CTRL_ANTIALIAS_MASK 0x00300 /* Bit [9:8] anti-alias mode */

#define	VI_CTRL_DITHER_FILTER_ON 0x10000 /* Bit 16: dither-filter mode */

#define	VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */

#define	VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */

#define	VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */

#define	AI_BASE_REG 0x04500000

#define	AI_DRAM_ADDR_REG (AI_BASE_REG+0x00) /* R0: DRAM address */

#define	AI_LEN_REG (AI_BASE_REG+0x04) /* R1: Length */

#define	AI_CONTROL_REG (AI_BASE_REG+0x08) /* R2: DMA Control */

#define	AI_STATUS_REG (AI_BASE_REG+0x0C) /* R3: Status */

#define	AI_DACRATE_REG (AI_BASE_REG+0x10) /* R4: DAC rate 14-lsb*/

#define	AI_BITRATE_REG (AI_BASE_REG+0x14) /* R5: Bit rate 4-lsb */

#define	AI_CONTROL_DMA_ON 0x01 /* LSB = 1: DMA enable*/

#define	AI_CONTROL_DMA_OFF 0x00 /* LSB = 1: DMA enable*/

#define	AI_STATUS_FIFO_FULL 0x80000000 /* Bit 31: full */

#define	AI_STATUS_DMA_BUSY 0x40000000 /* Bit 30: busy */

#define	AI_MAX_DAC_RATE 16384 /* 14-bit+1 */

#define	AI_MIN_DAC_RATE 132

#define	AI_MAX_BIT_RATE 16 /* 4-bit+1 */

#define	AI_MIN_BIT_RATE 2

#define	AI_NTSC_MAX_FREQ 368000 /* 368 KHz */

#define	AI_NTSC_MIN_FREQ 3000 /* 3 KHz ~ 2971 Hz */

#define	AI_PAL_MAX_FREQ 376000 /* 376 KHz */

#define	AI_PAL_MIN_FREQ 3050 /* 3 KHz ~ 3031 Hz */

#define	AI_MPAL_MAX_FREQ 368000 /* 368 KHz */

#define	AI_MPAL_MIN_FREQ 3000 /* 3 KHz ~ 2968 Hz */

#define	PI_BASE_REG 0x04600000

#define	PI_DRAM_ADDR_REG (PI_BASE_REG+0x00) /* DRAM address */

#define	PI_CART_ADDR_REG (PI_BASE_REG+0x04)

#define	PI_RD_LEN_REG (PI_BASE_REG+0x08)

#define	PI_WR_LEN_REG (PI_BASE_REG+0x0C)

#define	PI_STATUS_REG (PI_BASE_REG+0x10)

#define	PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14)

#define	PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18)

#define	PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */

#define	PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20)

#define	PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */

#define	PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */

#define	PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */

#define	PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */

#define	PI_DOMAIN1_REG PI_BSD_DOM1_LAT_REG

#define	PI_DOMAIN2_REG PI_BSD_DOM2_LAT_REG

#define	PI_DOM_LAT_OFS 0x00

#define	PI_DOM_PWD_OFS 0x04

#define	PI_DOM_PGS_OFS 0x08

#define	PI_DOM_RLS_OFS 0x0C

#define	PI_STATUS_ERROR 0x04

#define	PI_STATUS_IO_BUSY 0x02

#define	PI_STATUS_DMA_BUSY 0x01

#define	PI_STATUS_RESET 0x01

#define	PI_SET_RESET PI_STATUS_RESET

#define	PI_STATUS_CLR_INTR 0x02

#define	PI_CLR_INTR PI_STATUS_CLR_INTR

#define	PI_DMA_BUFFER_SIZE 128

#define	PI_DOM1_ADDR1 0x06000000 /* to 0x07FFFFFF */

#define	PI_DOM1_ADDR2 0x10000000 /* to 0x1FBFFFFF */

#define	PI_DOM1_ADDR3 0x1FD00000 /* to 0x7FFFFFFF */

#define	PI_DOM2_ADDR1 0x05000000 /* to 0x05FFFFFF */

#define	PI_DOM2_ADDR2 0x08000000 /* to 0x0FFFFFFF */

#define	RI_BASE_REG 0x04700000

#define	RI_MODE_REG (RI_BASE_REG+0x00)

#define	RI_CONFIG_REG (RI_BASE_REG+0x04)

#define	RI_CURRENT_LOAD_REG (RI_BASE_REG+0x08)

#define	RI_SELECT_REG (RI_BASE_REG+0x0C)

#define	RI_REFRESH_REG (RI_BASE_REG+0x10)

#define	RI_COUNT_REG RI_REFRESH_REG

#define	RI_LATENCY_REG (RI_BASE_REG+0x14)

#define	RI_RERROR_REG (RI_BASE_REG+0x18)

#define	RI_WERROR_REG (RI_BASE_REG+0x1C)

#define	SI_BASE_REG 0x04800000

#define	SI_DRAM_ADDR_REG (SI_BASE_REG+0x00) /* R0: DRAM address */

#define	SI_PIF_ADDR_RD64B_REG (SI_BASE_REG+0x04) /* R1: 64B PIF->DRAM */

#define	SI_PIF_ADDR_WR64B_REG (SI_BASE_REG+0x10) /* R4: 64B DRAM->PIF */

#define	SI_STATUS_REG (SI_BASE_REG+0x18) /* R6: Status */

#define	SI_STATUS_DMA_BUSY 0x0001

#define	SI_STATUS_RD_BUSY 0x0002

#define	SI_STATUS_DMA_ERROR 0x0008

#define	SI_STATUS_INTERRUPT 0x1000

#define	GIO_BASE_REG 0x18000000

#define	GIO_GIO_INTR_REG (GIO_BASE_REG+0x000)

#define	GIO_GIO_SYNC_REG (GIO_BASE_REG+0x400)

#define	GIO_CART_INTR_REG (GIO_BASE_REG+0x800)

Macro Definition Documentation

◆ AI_BASE_REG

#define AI_BASE_REG 0x04500000

◆ AI_BITRATE_REG

#define AI_BITRATE_REG (AI_BASE_REG+0x14) /* R5: Bit rate 4-lsb */

◆ AI_CONTROL_DMA_OFF

#define AI_CONTROL_DMA_OFF 0x00 /* LSB = 1: DMA enable*/

◆ AI_CONTROL_DMA_ON

#define AI_CONTROL_DMA_ON 0x01 /* LSB = 1: DMA enable*/

◆ AI_CONTROL_REG

#define AI_CONTROL_REG (AI_BASE_REG+0x08) /* R2: DMA Control */

◆ AI_DACRATE_REG

#define AI_DACRATE_REG (AI_BASE_REG+0x10) /* R4: DAC rate 14-lsb*/

◆ AI_DRAM_ADDR_REG

#define AI_DRAM_ADDR_REG (AI_BASE_REG+0x00) /* R0: DRAM address */

◆ AI_LEN_REG

#define AI_LEN_REG (AI_BASE_REG+0x04) /* R1: Length */

◆ AI_MAX_BIT_RATE

#define AI_MAX_BIT_RATE 16 /* 4-bit+1 */

◆ AI_MAX_DAC_RATE

#define AI_MAX_DAC_RATE 16384 /* 14-bit+1 */

◆ AI_MIN_BIT_RATE

#define AI_MIN_BIT_RATE 2

◆ AI_MIN_DAC_RATE

#define AI_MIN_DAC_RATE 132

◆ AI_MPAL_MAX_FREQ

#define AI_MPAL_MAX_FREQ 368000 /* 368 KHz */

◆ AI_MPAL_MIN_FREQ

#define AI_MPAL_MIN_FREQ 3000 /* 3 KHz ~ 2968 Hz */

◆ AI_NTSC_MAX_FREQ

#define AI_NTSC_MAX_FREQ 368000 /* 368 KHz */

◆ AI_NTSC_MIN_FREQ

#define AI_NTSC_MIN_FREQ 3000 /* 3 KHz ~ 2971 Hz */

◆ AI_PAL_MAX_FREQ

#define AI_PAL_MAX_FREQ 376000 /* 376 KHz */

◆ AI_PAL_MIN_FREQ

#define AI_PAL_MIN_FREQ 3050 /* 3 KHz ~ 3031 Hz */

◆ AI_STATUS_DMA_BUSY

#define AI_STATUS_DMA_BUSY 0x40000000 /* Bit 30: busy */

◆ AI_STATUS_FIFO_FULL

#define AI_STATUS_FIFO_FULL 0x80000000 /* Bit 31: full */

◆ AI_STATUS_REG

#define AI_STATUS_REG (AI_BASE_REG+0x0C) /* R3: Status */

◆ CHNL_ERR_COLLISION

#define CHNL_ERR_COLLISION 0x40 /* Bit 6 (Tx): Collision error */

◆ CHNL_ERR_FRAME

#define CHNL_ERR_FRAME 0x80 /* Bit 7 (Tx): Frame error */

◆ CHNL_ERR_MASK

#define CHNL_ERR_MASK 0xC0 /* Bit 6-7: channel errors */

◆ CHNL_ERR_NORESP

#define CHNL_ERR_NORESP 0x80 /* Bit 7 (Rx): No response error */

◆ CHNL_ERR_OVERRUN

#define CHNL_ERR_OVERRUN 0x40 /* Bit 6 (Rx): Overrun error */

◆ DEVICE_TYPE_64DD

#define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */

◆ DEVICE_TYPE_BULK

#define DEVICE_TYPE_BULK 1 /* ROM bulk */

◆ DEVICE_TYPE_CART

#define DEVICE_TYPE_CART 0 /* ROM cartridge */

◆ DEVICE_TYPE_SRAM

#define DEVICE_TYPE_SRAM 3 /* SRAM */

◆ DPC_BASE_REG

#define DPC_BASE_REG 0x04100000

◆ DPC_BUFBUSY_REG

#define DPC_BUFBUSY_REG (DPC_BASE_REG+0x14)

◆ DPC_CLOCK_REG

#define DPC_CLOCK_REG (DPC_BASE_REG+0x10)

◆ DPC_CLR_CLOCK_CTR

#define DPC_CLR_CLOCK_CTR 0x0200 /* Bit 9: clear clock ctr */

◆ DPC_CLR_CMD_CTR

#define DPC_CLR_CMD_CTR 0x0100 /* Bit 8: clear cmd ctr */

◆ DPC_CLR_FLUSH

#define DPC_CLR_FLUSH 0x0010 /* Bit 4: clear flush */

◆ DPC_CLR_FREEZE

#define DPC_CLR_FREEZE 0x0004 /* Bit 2: clear freeze */

◆ DPC_CLR_PIPE_CTR

#define DPC_CLR_PIPE_CTR 0x0080 /* Bit 7: clear pipe ctr */

◆ DPC_CLR_TMEM_CTR

#define DPC_CLR_TMEM_CTR 0x0040 /* Bit 6: clear tmem ctr */

◆ DPC_CLR_XBUS_DMEM_DMA

#define DPC_CLR_XBUS_DMEM_DMA 0x0001 /* Bit 0: clear xbus_dmem_dma */

◆ DPC_CURRENT_REG

#define DPC_CURRENT_REG (DPC_BASE_REG+0x08)

◆ DPC_END_REG

#define DPC_END_REG (DPC_BASE_REG+0x04)

◆ DPC_PIPEBUSY_REG

#define DPC_PIPEBUSY_REG (DPC_BASE_REG+0x18)

◆ DPC_SET_FLUSH

#define DPC_SET_FLUSH 0x0020 /* Bit 5: set flush */

◆ DPC_SET_FREEZE

#define DPC_SET_FREEZE 0x0008 /* Bit 3: set freeze */

◆ DPC_SET_XBUS_DMEM_DMA

#define DPC_SET_XBUS_DMEM_DMA 0x0002 /* Bit 1: set xbus_dmem_dma */

◆ DPC_START_REG

#define DPC_START_REG (DPC_BASE_REG+0x00)

◆ DPC_STATUS_CBUF_READY

#define DPC_STATUS_CBUF_READY 0x080 /* Bit 7: cbuf ready */

◆ DPC_STATUS_CMD_BUSY

#define DPC_STATUS_CMD_BUSY 0x040 /* Bit 6: cmd busy */

◆ DPC_STATUS_DMA_BUSY

#define DPC_STATUS_DMA_BUSY 0x100 /* Bit 8: dma busy */

◆ DPC_STATUS_END_VALID

#define DPC_STATUS_END_VALID 0x200 /* Bit 9: end valid */

◆ DPC_STATUS_FLUSH

#define DPC_STATUS_FLUSH 0x004 /* Bit 2: flush */

◆ DPC_STATUS_FREEZE

#define DPC_STATUS_FREEZE 0x002 /* Bit 1: freeze */

◆ DPC_STATUS_PIPE_BUSY

#define DPC_STATUS_PIPE_BUSY 0x020 /* Bit 5: pipe busy */

◆ DPC_STATUS_REG

#define DPC_STATUS_REG (DPC_BASE_REG+0x0C)

◆ DPC_STATUS_START_GCLK

#define DPC_STATUS_START_GCLK 0x008 /* Bit 3: start gclk */

◆ DPC_STATUS_START_VALID

#define DPC_STATUS_START_VALID 0x400 /* Bit 10: start valid */

◆ DPC_STATUS_TMEM_BUSY

#define DPC_STATUS_TMEM_BUSY 0x010 /* Bit 4: tmem busy */

◆ DPC_STATUS_XBUS_DMEM_DMA

#define DPC_STATUS_XBUS_DMEM_DMA 0x001 /* Bit 0: xbus_dmem_dma */

◆ DPC_TMEM_REG

#define DPC_TMEM_REG (DPC_BASE_REG+0x1C)

◆ DPS_BASE_REG

#define DPS_BASE_REG 0x04200000

◆ DPS_BUFTEST_ADDR_REG

#define DPS_BUFTEST_ADDR_REG (DPS_BASE_REG+0x08)

◆ DPS_BUFTEST_DATA_REG

#define DPS_BUFTEST_DATA_REG (DPS_BASE_REG+0x0C)

◆ DPS_TBIST_CHECK

#define DPS_TBIST_CHECK 0x01 /* Bit 0: BIST check */

◆ DPS_TBIST_CLEAR

#define DPS_TBIST_CLEAR 0x04 /* Bit 2: BIST clear */

◆ DPS_TBIST_DONE

#define DPS_TBIST_DONE 0x004 /* Bit 2: BIST done */

◆ DPS_TBIST_FAILED

#define DPS_TBIST_FAILED 0x7F8 /* Bit [10:3]: BIST fail */

◆ DPS_TBIST_GO

#define DPS_TBIST_GO 0x02 /* Bit 1: BIST go */

◆ DPS_TBIST_REG

#define DPS_TBIST_REG (DPS_BASE_REG+0x00)

◆ DPS_TEST_MODE_REG

#define DPS_TEST_MODE_REG (DPS_BASE_REG+0x04)

◆ GIO_BASE_REG

#define GIO_BASE_REG 0x18000000

◆ GIO_CART_INTR_REG

#define GIO_CART_INTR_REG (GIO_BASE_REG+0x800)

◆ GIO_GIO_INTR_REG

#define GIO_GIO_INTR_REG (GIO_BASE_REG+0x000)

◆ GIO_GIO_SYNC_REG

#define GIO_GIO_SYNC_REG (GIO_BASE_REG+0x400)

◆ MI_BASE_REG

#define MI_BASE_REG 0x04300000

◆ MI_CLR_DP_INTR

#define MI_CLR_DP_INTR 0x0800 /* Bit 11: clear dp interrupt */

◆ MI_CLR_EBUS

#define MI_CLR_EBUS 0x0200 /* Bit 9: clear ebus test */

◆ MI_CLR_INIT

#define MI_CLR_INIT 0x0080 /* Bit 7: clear init mode */

◆ MI_CLR_RDRAM

#define MI_CLR_RDRAM 0x1000 /* Bit 12: clear RDRAM reg */

◆ MI_INIT_MODE_REG

#define MI_INIT_MODE_REG (MI_BASE_REG+0x00)

◆ MI_INTR_AI

#define MI_INTR_AI 0x04 /* Bit 2: AI intr */

◆ MI_INTR_DP

#define MI_INTR_DP 0x20 /* Bit 5: DP intr */

◆ MI_INTR_MASK_AI

#define MI_INTR_MASK_AI 0x04 /* Bit 2: AI intr mask */

◆ MI_INTR_MASK_CLR_AI

#define MI_INTR_MASK_CLR_AI 0x0010 /* Bit 4: clear AI mask */

◆ MI_INTR_MASK_CLR_DP

#define MI_INTR_MASK_CLR_DP 0x0400 /* Bit 10: clear DP mask */

◆ MI_INTR_MASK_CLR_PI

#define MI_INTR_MASK_CLR_PI 0x0100 /* Bit 8: clear PI mask */

◆ MI_INTR_MASK_CLR_SI

#define MI_INTR_MASK_CLR_SI 0x0004 /* Bit 2: clear SI mask */

◆ MI_INTR_MASK_CLR_SP

#define MI_INTR_MASK_CLR_SP 0x0001 /* Bit 0: clear SP mask */

◆ MI_INTR_MASK_CLR_VI

#define MI_INTR_MASK_CLR_VI 0x0040 /* Bit 6: clear VI mask */

◆ MI_INTR_MASK_DP

#define MI_INTR_MASK_DP 0x20 /* Bit 5: DP intr mask */

◆ MI_INTR_MASK_PI

#define MI_INTR_MASK_PI 0x10 /* Bit 4: PI intr mask */

◆ MI_INTR_MASK_REG

#define MI_INTR_MASK_REG (MI_BASE_REG+0x0C)

◆ MI_INTR_MASK_SET_AI

#define MI_INTR_MASK_SET_AI 0x0020 /* Bit 5: set AI mask */

◆ MI_INTR_MASK_SET_DP

#define MI_INTR_MASK_SET_DP 0x0800 /* Bit 11: set DP mask */

◆ MI_INTR_MASK_SET_PI

#define MI_INTR_MASK_SET_PI 0x0200 /* Bit 9: set PI mask */

◆ MI_INTR_MASK_SET_SI

#define MI_INTR_MASK_SET_SI 0x0008 /* Bit 3: set SI mask */

◆ MI_INTR_MASK_SET_SP

#define MI_INTR_MASK_SET_SP 0x0002 /* Bit 1: set SP mask */

◆ MI_INTR_MASK_SET_VI

#define MI_INTR_MASK_SET_VI 0x0080 /* Bit 7: set VI mask */

◆ MI_INTR_MASK_SI

#define MI_INTR_MASK_SI 0x02 /* Bit 1: SI intr mask */

◆ MI_INTR_MASK_SP

#define MI_INTR_MASK_SP 0x01 /* Bit 0: SP intr mask */

◆ MI_INTR_MASK_VI

#define MI_INTR_MASK_VI 0x08 /* Bit 3: VI intr mask */

◆ MI_INTR_PI

#define MI_INTR_PI 0x10 /* Bit 4: PI intr */

◆ MI_INTR_REG

#define MI_INTR_REG (MI_BASE_REG+0x08)

◆ MI_INTR_SI

#define MI_INTR_SI 0x02 /* Bit 1: SI intr */

◆ MI_INTR_SP

#define MI_INTR_SP 0x01 /* Bit 0: SP intr */

◆ MI_INTR_VI

#define MI_INTR_VI 0x08 /* Bit 3: VI intr */

◆ MI_MODE_EBUS

#define MI_MODE_EBUS 0x0100 /* Bit 8: ebus test mode */

◆ MI_MODE_INIT

#define MI_MODE_INIT 0x0080 /* Bit 7: init mode */

◆ MI_MODE_RDRAM

#define MI_MODE_RDRAM 0x0200 /* Bit 9: RDRAM reg mode */

◆ MI_MODE_REG

#define MI_MODE_REG MI_INIT_MODE_REG

◆ MI_NOOP_REG

#define MI_NOOP_REG MI_VERSION_REG

◆ MI_SET_EBUS

#define MI_SET_EBUS 0x0400 /* Bit 10: set ebus test mode */

◆ MI_SET_INIT

#define MI_SET_INIT 0x0100 /* Bit 8: set init mode */

◆ MI_SET_RDRAM

#define MI_SET_RDRAM 0x2000 /* Bit 13: set RDRAM reg mode */

◆ MI_VERSION_REG

#define MI_VERSION_REG (MI_BASE_REG+0x04)

◆ PI_BASE_REG

#define PI_BASE_REG 0x04600000

◆ PI_BSD_DOM1_LAT_REG

#define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14)

◆ PI_BSD_DOM1_PGS_REG

#define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */

◆ PI_BSD_DOM1_PWD_REG

#define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18)

◆ PI_BSD_DOM1_RLS_REG

#define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20)

◆ PI_BSD_DOM2_LAT_REG

#define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */

◆ PI_BSD_DOM2_PGS_REG

#define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */

◆ PI_BSD_DOM2_PWD_REG

#define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */

◆ PI_BSD_DOM2_RLS_REG

#define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */

◆ PI_CART_ADDR_REG

#define PI_CART_ADDR_REG (PI_BASE_REG+0x04)

◆ PI_CLR_INTR

#define PI_CLR_INTR PI_STATUS_CLR_INTR

◆ PI_DMA_BUFFER_SIZE

#define PI_DMA_BUFFER_SIZE 128

◆ PI_DOM1_ADDR1

#define PI_DOM1_ADDR1 0x06000000 /* to 0x07FFFFFF */

◆ PI_DOM1_ADDR2

#define PI_DOM1_ADDR2 0x10000000 /* to 0x1FBFFFFF */

◆ PI_DOM1_ADDR3

#define PI_DOM1_ADDR3 0x1FD00000 /* to 0x7FFFFFFF */

◆ PI_DOM2_ADDR1

#define PI_DOM2_ADDR1 0x05000000 /* to 0x05FFFFFF */

◆ PI_DOM2_ADDR2

#define PI_DOM2_ADDR2 0x08000000 /* to 0x0FFFFFFF */

◆ PI_DOM_LAT_OFS

#define PI_DOM_LAT_OFS 0x00

◆ PI_DOM_PGS_OFS

#define PI_DOM_PGS_OFS 0x08

◆ PI_DOM_PWD_OFS

#define PI_DOM_PWD_OFS 0x04

◆ PI_DOM_RLS_OFS

#define PI_DOM_RLS_OFS 0x0C

◆ PI_DOMAIN1_REG

#define PI_DOMAIN1_REG PI_BSD_DOM1_LAT_REG

◆ PI_DOMAIN2_REG

#define PI_DOMAIN2_REG PI_BSD_DOM2_LAT_REG

◆ PI_DRAM_ADDR_REG

#define PI_DRAM_ADDR_REG (PI_BASE_REG+0x00) /* DRAM address */

◆ PI_RD_LEN_REG

#define PI_RD_LEN_REG (PI_BASE_REG+0x08)

◆ PI_SET_RESET

#define PI_SET_RESET PI_STATUS_RESET

◆ PI_STATUS_CLR_INTR

#define PI_STATUS_CLR_INTR 0x02

◆ PI_STATUS_DMA_BUSY

#define PI_STATUS_DMA_BUSY 0x01

◆ PI_STATUS_ERROR

#define PI_STATUS_ERROR 0x04

◆ PI_STATUS_IO_BUSY

#define PI_STATUS_IO_BUSY 0x02

◆ PI_STATUS_REG

#define PI_STATUS_REG (PI_BASE_REG+0x10)

◆ PI_STATUS_RESET

#define PI_STATUS_RESET 0x01

◆ PI_WR_LEN_REG

#define PI_WR_LEN_REG (PI_BASE_REG+0x0C)

◆ PIF_RAM_END

#define PIF_RAM_END 0x1FC007FF

◆ PIF_RAM_START

#define PIF_RAM_START 0x1FC007C0

◆ PIF_ROM_END

#define PIF_ROM_END 0x1FC007BF

◆ PIF_ROM_START

#define PIF_ROM_START 0x1FC00000

◆ RDRAM_0_BASE_ADDRESS

#define RDRAM_0_BASE_ADDRESS (RDRAM_0_DEVICE_ID*RDRAM_LENGTH)

◆ RDRAM_0_CONFIG

#define RDRAM_0_CONFIG 0x00000

◆ RDRAM_0_DEVICE_ID

#define RDRAM_0_DEVICE_ID 0

◆ RDRAM_0_END

#define RDRAM_0_END 0x001FFFFF

◆ RDRAM_0_START

#define RDRAM_0_START 0x00000000

◆ RDRAM_1_BASE_ADDRESS

#define RDRAM_1_BASE_ADDRESS (RDRAM_1_DEVICE_ID*RDRAM_LENGTH)

◆ RDRAM_1_CONFIG

#define RDRAM_1_CONFIG 0x00400

◆ RDRAM_1_DEVICE_ID

#define RDRAM_1_DEVICE_ID 1

◆ RDRAM_1_END

#define RDRAM_1_END 0x003FFFFF

◆ RDRAM_1_START

#define RDRAM_1_START 0x00200000

◆ RDRAM_ACTIVE_MODE

#define RDRAM_ACTIVE_MODE 1

◆ RDRAM_ADDR_SELECT_REG

#define RDRAM_ADDR_SELECT_REG (RDRAM_BASE_REG+0x20)

◆ RDRAM_BASE_REG

#define RDRAM_BASE_REG 0x03F00000

◆ RDRAM_CONFIG_REG

#define RDRAM_CONFIG_REG (RDRAM_BASE_REG+0x00)

◆ RDRAM_DELAY_REG

#define RDRAM_DELAY_REG (RDRAM_BASE_REG+0x08)

◆ RDRAM_DEVICE_ID_REG

#define RDRAM_DEVICE_ID_REG (RDRAM_BASE_REG+0x04)

◆ RDRAM_DEVICE_MANUF_REG

#define RDRAM_DEVICE_MANUF_REG (RDRAM_BASE_REG+0x24)

◆ RDRAM_DEVICE_TYPE_REG

#define RDRAM_DEVICE_TYPE_REG (RDRAM_BASE_REG+0x00)

◆ RDRAM_END

#define RDRAM_END RDRAM_1_END

◆ RDRAM_GLOBAL_CONFIG

#define RDRAM_GLOBAL_CONFIG 0x80000

◆ RDRAM_LENGTH

#define RDRAM_LENGTH (2*512*2048)

◆ RDRAM_MIN_INTERVAL_REG

#define RDRAM_MIN_INTERVAL_REG (RDRAM_BASE_REG+0x1c)

◆ RDRAM_MODE_REG

#define RDRAM_MODE_REG (RDRAM_BASE_REG+0x0c)

◆ RDRAM_RAS_INTERVAL_REG

#define RDRAM_RAS_INTERVAL_REG (RDRAM_BASE_REG+0x18)

◆ RDRAM_REF_INTERVAL_REG

#define RDRAM_REF_INTERVAL_REG (RDRAM_BASE_REG+0x10)

◆ RDRAM_REF_ROW_REG

#define RDRAM_REF_ROW_REG (RDRAM_BASE_REG+0x14)

◆ RDRAM_RESET_MODE

#define RDRAM_RESET_MODE 0

◆ RDRAM_STANDBY_MODE

#define RDRAM_STANDBY_MODE 2

◆ RDRAM_START

#define RDRAM_START RDRAM_0_START

◆ RI_BASE_REG

#define RI_BASE_REG 0x04700000

◆ RI_CONFIG_REG

#define RI_CONFIG_REG (RI_BASE_REG+0x04)

◆ RI_COUNT_REG

#define RI_COUNT_REG RI_REFRESH_REG

◆ RI_CURRENT_LOAD_REG

#define RI_CURRENT_LOAD_REG (RI_BASE_REG+0x08)

◆ RI_LATENCY_REG

#define RI_LATENCY_REG (RI_BASE_REG+0x14)

◆ RI_MODE_REG

#define RI_MODE_REG (RI_BASE_REG+0x00)

◆ RI_REFRESH_REG

#define RI_REFRESH_REG (RI_BASE_REG+0x10)

◆ RI_RERROR_REG

#define RI_RERROR_REG (RI_BASE_REG+0x18)

◆ RI_SELECT_REG

#define RI_SELECT_REG (RI_BASE_REG+0x0C)

◆ RI_WERROR_REG

#define RI_WERROR_REG (RI_BASE_REG+0x1C)

◆ SI_BASE_REG

#define SI_BASE_REG 0x04800000

◆ SI_DRAM_ADDR_REG

#define SI_DRAM_ADDR_REG (SI_BASE_REG+0x00) /* R0: DRAM address */

◆ SI_PIF_ADDR_RD64B_REG

#define SI_PIF_ADDR_RD64B_REG (SI_BASE_REG+0x04) /* R1: 64B PIF->DRAM */

◆ SI_PIF_ADDR_WR64B_REG

#define SI_PIF_ADDR_WR64B_REG (SI_BASE_REG+0x10) /* R4: 64B DRAM->PIF */

◆ SI_STATUS_DMA_BUSY

#define SI_STATUS_DMA_BUSY 0x0001

◆ SI_STATUS_DMA_ERROR

#define SI_STATUS_DMA_ERROR 0x0008

◆ SI_STATUS_INTERRUPT

#define SI_STATUS_INTERRUPT 0x1000

◆ SI_STATUS_RD_BUSY

#define SI_STATUS_RD_BUSY 0x0002

◆ SI_STATUS_REG

#define SI_STATUS_REG (SI_BASE_REG+0x18) /* R6: Status */

◆ SP_BASE_REG

#define SP_BASE_REG 0x04040000

◆ SP_CLR_BROKE

#define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */

◆ SP_CLR_CPUSIGNAL

#define SP_CLR_CPUSIGNAL SP_CLR_SIG4

◆ SP_CLR_HALT

#define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */

◆ SP_CLR_INTR

#define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */

◆ SP_CLR_INTR_BREAK

#define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */

◆ SP_CLR_RSPSIGNAL

#define SP_CLR_RSPSIGNAL SP_CLR_SIG3

◆ SP_CLR_SIG0

#define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */

◆ SP_CLR_SIG1

#define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */

◆ SP_CLR_SIG2

#define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */

◆ SP_CLR_SIG3

#define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */

◆ SP_CLR_SIG4

#define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */

◆ SP_CLR_SIG5

#define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */

◆ SP_CLR_SIG6

#define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */

◆ SP_CLR_SIG7

#define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */

◆ SP_CLR_SSTEP

#define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */

◆ SP_CLR_TASKDONE

#define SP_CLR_TASKDONE SP_CLR_SIG2

◆ SP_CLR_YIELD

#define SP_CLR_YIELD SP_CLR_SIG0

◆ SP_CLR_YIELDED

#define SP_CLR_YIELDED SP_CLR_SIG1

◆ SP_DMA_BUSY_REG

#define SP_DMA_BUSY_REG (SP_BASE_REG+0x18)

◆ SP_DMA_DMEM

#define SP_DMA_DMEM 0x0000 /* Bit 12: 0=DMEM, 1=IMEM */

◆ SP_DMA_FULL_REG

#define SP_DMA_FULL_REG (SP_BASE_REG+0x14)

◆ SP_DMA_IMEM

#define SP_DMA_IMEM 0x1000 /* Bit 12: 0=DMEM, 1=IMEM */

◆ SP_DMEM_END

#define SP_DMEM_END 0x04000FFF

◆ SP_DMEM_START

#define SP_DMEM_START 0x04000000 /* read/write */

◆ SP_DRAM_ADDR_REG

#define SP_DRAM_ADDR_REG (SP_BASE_REG+0x04) /* Slave */

◆ SP_IBIST_CHECK

#define SP_IBIST_CHECK 0x01 /* Bit 0: BIST check */

◆ SP_IBIST_CLEAR

#define SP_IBIST_CLEAR 0x04 /* Bit 2: BIST clear */

◆ SP_IBIST_DONE

#define SP_IBIST_DONE 0x04 /* Bit 2: BIST done */

◆ SP_IBIST_FAILED

#define SP_IBIST_FAILED 0x78 /* Bit [6:3]: BIST fail */

◆ SP_IBIST_GO

#define SP_IBIST_GO 0x02 /* Bit 1: BIST go */

◆ SP_IBIST_REG

#define SP_IBIST_REG 0x04080004

◆ SP_IMEM_END

#define SP_IMEM_END 0x04001FFF

◆ SP_IMEM_START

#define SP_IMEM_START 0x04001000 /* read/write */

◆ SP_MEM_ADDR_REG

#define SP_MEM_ADDR_REG (SP_BASE_REG+0x00) /* Master */

◆ SP_PC_REG

#define SP_PC_REG 0x04080000

◆ SP_RD_LEN_REG

#define SP_RD_LEN_REG (SP_BASE_REG+0x08) /* R/W: read len */

◆ SP_SEMAPHORE_REG

#define SP_SEMAPHORE_REG (SP_BASE_REG+0x1C)

◆ SP_SET_CPUSIGNAL

#define SP_SET_CPUSIGNAL SP_SET_SIG4

◆ SP_SET_HALT

#define SP_SET_HALT 0x00002 /* Bit 1: set halt */

◆ SP_SET_INTR

#define SP_SET_INTR 0x00010 /* Bit 4: set intr */

◆ SP_SET_INTR_BREAK

#define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */

◆ SP_SET_RSPSIGNAL

#define SP_SET_RSPSIGNAL SP_SET_SIG3

◆ SP_SET_SIG0

#define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */

◆ SP_SET_SIG1

#define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */

◆ SP_SET_SIG2

#define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */

◆ SP_SET_SIG3

#define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */

◆ SP_SET_SIG4

#define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */

◆ SP_SET_SIG5

#define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */

◆ SP_SET_SIG6

#define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */

◆ SP_SET_SIG7

#define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */

◆ SP_SET_SSTEP

#define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */

◆ SP_SET_TASKDONE

#define SP_SET_TASKDONE SP_SET_SIG2

◆ SP_SET_YIELD

#define SP_SET_YIELD SP_SET_SIG0

◆ SP_SET_YIELDED

#define SP_SET_YIELDED SP_SET_SIG1

◆ SP_STATUS_BROKE

#define SP_STATUS_BROKE 0x002 /* Bit 1: broke */

◆ SP_STATUS_CPUSIGNAL

#define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4

◆ SP_STATUS_DMA_BUSY

#define SP_STATUS_DMA_BUSY 0x004 /* Bit 2: dma busy */

◆ SP_STATUS_DMA_FULL

#define SP_STATUS_DMA_FULL 0x008 /* Bit 3: dma full */

◆ SP_STATUS_HALT

#define SP_STATUS_HALT 0x001 /* Bit 0: halt */

◆ SP_STATUS_INTR_BREAK

#define SP_STATUS_INTR_BREAK 0x040 /* Bit 6: interrupt on break */

◆ SP_STATUS_IO_FULL

#define SP_STATUS_IO_FULL 0x010 /* Bit 4: io full */

◆ SP_STATUS_REG

#define SP_STATUS_REG (SP_BASE_REG+0x10)

◆ SP_STATUS_RSPSIGNAL

#define SP_STATUS_RSPSIGNAL SP_STATUS_SIG3

◆ SP_STATUS_SIG0

#define SP_STATUS_SIG0 0x080 /* Bit 7: signal 0 set */

◆ SP_STATUS_SIG1

#define SP_STATUS_SIG1 0x100 /* Bit 8: signal 1 set */

◆ SP_STATUS_SIG2

#define SP_STATUS_SIG2 0x200 /* Bit 9: signal 2 set */

◆ SP_STATUS_SIG3

#define SP_STATUS_SIG3 0x400 /* Bit 10: signal 3 set */

◆ SP_STATUS_SIG4

#define SP_STATUS_SIG4 0x800 /* Bit 11: signal 4 set */

◆ SP_STATUS_SIG5

#define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */

◆ SP_STATUS_SIG6

#define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */

◆ SP_STATUS_SIG7

#define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */

◆ SP_STATUS_SSTEP

#define SP_STATUS_SSTEP 0x020 /* Bit 5: single step */

◆ SP_STATUS_TASKDONE

#define SP_STATUS_TASKDONE SP_STATUS_SIG2

◆ SP_STATUS_YIELD

#define SP_STATUS_YIELD SP_STATUS_SIG0

◆ SP_STATUS_YIELDED

#define SP_STATUS_YIELDED SP_STATUS_SIG1

◆ SP_WR_LEN_REG

#define SP_WR_LEN_REG (SP_BASE_REG+0x0C) /* R/W: write len */

◆ VI_BASE_REG

#define VI_BASE_REG 0x04400000

◆ VI_BURST_REG

#define VI_BURST_REG (VI_BASE_REG+0x14)

◆ VI_CONTROL_REG

#define VI_CONTROL_REG VI_STATUS_REG

◆ VI_CTRL_ANTIALIAS_MASK

#define VI_CTRL_ANTIALIAS_MASK 0x00300 /* Bit [9:8] anti-alias mode */

◆ VI_CTRL_DITHER_FILTER_ON

#define VI_CTRL_DITHER_FILTER_ON 0x10000 /* Bit 16: dither-filter mode */

◆ VI_CTRL_DIVOT_ON

#define VI_CTRL_DIVOT_ON 0x00010 /* Bit 4: default = on */

◆ VI_CTRL_GAMMA_DITHER_ON

#define VI_CTRL_GAMMA_DITHER_ON 0x00004 /* Bit 2: default = on */

◆ VI_CTRL_GAMMA_ON

#define VI_CTRL_GAMMA_ON 0x00008 /* Bit 3: default = on */

◆ VI_CTRL_SERRATE_ON

#define VI_CTRL_SERRATE_ON 0x00040 /* Bit 6: on if interlaced */

◆ VI_CTRL_TYPE_16

#define VI_CTRL_TYPE_16 0x00002 /* Bit [1:0] pixel size: 16 bit */

◆ VI_CTRL_TYPE_32

#define VI_CTRL_TYPE_32 0x00003 /* Bit [1:0] pixel size: 32 bit */

◆ VI_CURRENT_REG

#define VI_CURRENT_REG (VI_BASE_REG+0x10)

◆ VI_DRAM_ADDR_REG

#define VI_DRAM_ADDR_REG VI_ORIGIN_REG

◆ VI_H_START_REG

#define VI_H_START_REG (VI_BASE_REG+0x24)

◆ VI_H_SYNC_LEAP_REG

#define VI_H_SYNC_LEAP_REG VI_LEAP_REG

◆ VI_H_SYNC_REG

#define VI_H_SYNC_REG (VI_BASE_REG+0x1C)

◆ VI_H_VIDEO_REG

#define VI_H_VIDEO_REG VI_H_START_REG

◆ VI_H_WIDTH_REG

#define VI_H_WIDTH_REG VI_WIDTH_REG

◆ VI_INTR_REG

#define VI_INTR_REG (VI_BASE_REG+0x0C)

◆ VI_LEAP_REG

#define VI_LEAP_REG (VI_BASE_REG+0x20)

◆ VI_MPAL_CLOCK

#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */

◆ VI_NTSC_CLOCK

#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */

◆ VI_ORIGIN_REG

#define VI_ORIGIN_REG (VI_BASE_REG+0x04)

◆ VI_PAL_CLOCK

#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */

◆ VI_STATUS_REG

#define VI_STATUS_REG (VI_BASE_REG+0x00)

◆ VI_TIMING_REG

#define VI_TIMING_REG VI_BURST_REG

◆ VI_V_BURST_REG

#define VI_V_BURST_REG (VI_BASE_REG+0x2C)

◆ VI_V_CURRENT_LINE_REG

#define VI_V_CURRENT_LINE_REG VI_CURRENT_REG

◆ VI_V_INTR_REG

#define VI_V_INTR_REG VI_INTR_REG

◆ VI_V_START_REG

#define VI_V_START_REG (VI_BASE_REG+0x28)

◆ VI_V_SYNC_REG

#define VI_V_SYNC_REG (VI_BASE_REG+0x18)

◆ VI_V_VIDEO_REG

#define VI_V_VIDEO_REG VI_V_START_REG

◆ VI_WIDTH_REG

#define VI_WIDTH_REG (VI_BASE_REG+0x08)

◆ VI_X_SCALE_REG

#define VI_X_SCALE_REG (VI_BASE_REG+0x30)

◆ VI_Y_SCALE_REG

#define VI_Y_SCALE_REG (VI_BASE_REG+0x34)

Macros